1. Field of the Invention
This invention relates generally to an improvement in synchronizing two clock domains, and more specifically to synchronizing two clock domains for repeatable testing of a data processing system.
2. Description of the Prior Art
In many data processing systems (e.g., computer systems, programmable electronic systems, telecommunication switching systems, control systems, and so forth) a link may be used to transfer data from one integrated circuit (IC) chip to another. If the IC chips are located far apart, they may operate with different clock sources, which have different clock phases and frequencies. In this case the link interface is considered asynchronous, and some type of synchronizing logic must be used between the two clock domains.
FIG. 1 illustrates a prior art approach for transmission and reception of data between a transmitting chip 130 and a receiving chip 132. External clock source A 160 outputs clock signal 4XCLKA 110 to internal divide-by-four clock generator 112, which outputs clock signal CLKA 114 to logic gate 116 and D flip-flop 124. Logic gate 116 outputs a clock signal to output driver 118, which outputs a clock signal LINK_CLKA 120 to receiving chip 132. Transmitting chip D flip-flop 124 receives data signal Data_A 122 and clock signal CLKA 114, and sends a data signal to output driver 126, which outputs a data signal LINK_Data 128 to receiving chip 132.
Receiving chip 132 receives a clock signal 4XCLKB 140 from external clock source B 162 with internal divide-by-four clock generator 142, which outputs clock signal CLKB 144 to D flip-flops 146 and 148. Receiver circuit 152 receives clock signal LINK_CLKA 120 and outputs a clock signal to D flip-flop 156. Receiver circuit 154 receives data signal LINK_Data 128 and outputs a data signal to D flip-flop 156. D flip-flop 156 outputs a data signal to D flip-flop 146, which outputs a data signal to D flip-flop 148. D flip-flop 148 outputs a data signal Data_B 150, which is synchronized to clock signal CLKB 144.
The prior art circuit of FIG. 1 shows a system where the two chip clocks (CLKA 114 and CLKB 144) are derived from two independent higher frequency clocks (4XCLKA 110 and 4XCLKB 140). Even if the 4X clocks are supposed to have identical frequencies, they will actually be slightly different. Furthermore, the divide by four clock generators may initialize differently. As a result, the rising edges of LINK_CLKA 120 and CLKB 144 may drift relative to each other. This may drop or stretch a cycle of Data_A when it appears at Data_B 150 output of synchronizing flip-flop 148 in receiving chip 132. There are well known techniques, including handshaking, first-in-first-out buffers, and Grey coding to deal with the uncertainties of crossing an asynchronous boundary. However, even with these techniques, the clock uncertainty means that a system test may fail differently on different test runs. It is desirable to have a repeatable test that always fails in the same way to simplify system debugging.
A first step to improve test repeatability is to send the 4XCLKA 110 signal to both IC chips and use it in place of 4XCLKB 140 on the receiving chip 132. Now the clock frequency for both IC chips is identical, but the phase of the two clocks is unknown. If the clock phase is such that the rising edges of LINK_CLKA 120 and CLKB 144 are far apart, the system will be repeatable during testing.
However, there are cases when the clock generators power up in a certain way and the delay in the clock signal 4XCLKA 110 cable is just right, that the rising edges of the LINK_CLKA 120 and CLKB 144 are very close to each other. In this case the synchronizer logic uncertainty may again cause unrepeatable test results.
It would be desirable to have the capability to repeatably test a system to determine the cause of failure. It would also be desirable to make a phase-unknown system design fully synchronous during normal operations, thereby avoiding some the problems encountered with asynchronous system designs.